1. Field of the Invention
The present invention relates to a structure of a semiconductor device, and more particularly to a structure of a DTMOSFET (Dynamic Threshold Metal Oxide Silicon Field Effect Transistor) formed on an SOI (Silicon On Insulator) substrate.
2. Description of the Background Art
A semiconductor device used for a portable device such as a notebook computer and a portable terminal is operated by a battery loaded in the portable device. Therefore, a portable device using a semiconductor device with less power consumption can be used for longer time with one charge of the battery. For this reason, it is desirable that a semiconductor device with less power consumption should be used in the portable device.
To reduce the power consumption of the semiconductor device, it is effective to reduce a power-supply voltage. For the power consumption of a CMOS digital circuit, for example, is in proportion to the square of the power-supply voltage. Since a drain current decreases when the power-supply voltage becomes three times as high as the threshold voltage or lower, the operating speed of the circuit largely decreases. Therefore, when the power-supply voltage is reduced, it is necessary to reduce the threshold voltage at the same time. A leak current flowing in a MOSFET when it is in an off state (when a gate-source voltage becomes the threshold voltage or lower), i.e., an off current, however, increases as the threshold voltage decreases. For this reason, when the threshold voltage is merely reduced, the power consumption in an off state increases. Further, a MOSFET used in a dynamic circuit, a memory cell array and the like sometimes causes malfunction when the threshold voltage is reduced.
Therefore, to reduce the power consumption of the semiconductor device without reducing the operating speed of the circuit, it is convenient that the threshold voltage can be set high in an off state and low in an on state, and as a structure to achieve this, a DTMOSFET is proposed (see U.S. Pat. No. 5,559,368).
FIG. 48 is a schematic diagram showing a structure of a DTMOSFET in the background art. An SOI substrate 101 has a multilayered structure in which a silicon substrate 102, a BOX (Buried OXide) layer 103 and a silicon layer 104 are layered in this order. The SOI substrate 101 can be formed by a well-known method such as the SIMOX (Separation by IMplanted OXygen) and the BESOI (Bonded and Etchback SOI).
In the silicon layer 104 formed are an n+-type source region 156 and an n+-type drain region 157 which are paired with a body region (channel region) 115 sandwiched therebetween. On the body region 115, a gate electrode 109 is formed with a gate oxide film 105 interposed therebetween. The gate electrode 109 has a multilayered structure in which a doped polysilicon layer 106, a metal nitride layer 107 and a metal layer 108 are layered on the gate oxide film 105 in this order. The characteristic feature of the DTMOSFET lies in electrical connection between the gate electrode 109 and the body region 115. A ground voltage is applied to the source region 156 and a power supply 158 such as a battery is connected to the drain region 157.
FIG. 49 is a plan view schematically showing the structure of the DTMOSFET in the background art. FIG. 50 is a cross section showing a cross-sectional structure taken along the line X100 of FIG. 49. Referring to FIG. 50, an STI (Shallow Trench Isolation) 117 is formed in the silicon layer 104 in the isolation region of the SOI substrate 101. A bottom surface of the STI 117 is in contact with an upper surface of the BOX layer 103.
In an element formation region of the SOI substrate 101 defined by the STI 117, a p+-type impurity diffusion region 111 adjacent to the STI 117 and the body region 115 adjacent to the impurity diffusion region 111 are formed in the silicon layer 104. On the body region 115, the gate oxide film 105 and the gate electrode 109 are formed and on the gate electrode 109, an interlayer insulating film 112 is formed.
On the impurity diffusion region 111, a metal plug 114 such as aluminum is formed. The metal plug 114 is also in contact with the gate electrode 109. The gate electrode 109 and the body region 115 are electrically connected to each other with the metal plug 114 and the impurity diffusion region 111 interposed therebetween.
Further, there may be a structure of the DTMOSFET, as shown in FIG. 51, where the metal plug 114 is so formed as to reach the upper surface of the BOX layer 103 and the metal plug 114 and the body region 115 are brought into direct contact with each other, instead of providing the impurity diffusion region 111 in the silicon layer 104 below the metal plug 114.
Referring to FIG. 49, the STI 117 is formed around the source region 156, the drain region 157, the body region 115 and the impurity diffusion region 111 with the bold line of the figure as a boundary.
Next, the electrical characteristics of the DTMOSFET will be discussed. In the following discussion, a DTMOSFET using the SOI substrate is referred to as xe2x80x9cSOI-DTMOSFETxe2x80x9d and an ordinary MOSFET in which the SOI substrate is used and the gate electrode and the body region are not connected to each other is referred to as xe2x80x9cSOI-MOSFETxe2x80x9d, for distinction. The SOI-DTMOSFET has excellent characteristics when a body voltage is 0.6 V or lower, as compared with the SOI-MOSFET. When the body voltage is 0.6 V or lower, it is possible to prevent a parasitic bipolar transistor using the source region 156 as an emitter, the body region 115 as a base and the drain region 157 as a collector from being driven and further prevent generation of power consumption accompanying the operation of the parasitic bipolar transistor.
Further, in a MOSFET using an ordinary bulk substrate, not the SOI substrate, (hereinafter, referred to as xe2x80x9cbulk-MOSFETxe2x80x9d), the same effect can be achieved by connecting the silicon substrate and the gate electrode to each other. In the SOI-DTMOSFET, however, respective bottom surfaces of the source region 156 and the drain region 157 can be brought into contact with the upper surface of the BOX layer 103, as shown in FIG. 48, and therefore the area of a pn junction formed of the n+-type source region 156, the n+-type drain region 157 and the p-type silicon layer 104 can be reduced. For this reason, in the SOI-DTMOSFET, a pn junction capacitance and a base current can be reduced as compared with the bulk-MOSFET.
Furthermore, since a depletion layer capacitance decreases as the pn junction capacitance decreases, as shown in FIG. 52, the SOI-DTMOSFET shows more excellent subthreshold characteristics than the bulk-MOSFET, regardless of whether NMOS or PMOS. Further, in the graph of FIG. 52, the horizontal axis indicates a gate voltage VG (V) and the vertical axis indicates the drain current ID (A), and xe2x80x9cSxe2x80x9d in the figure represents a subthreshold coefficient.
FIG. 53 is a graph showing a relation between a body bias voltage (the body voltage relative to the source) Vbs and the threshold voltage Vth in n-type SOI-MOSFET and SOI-DTMOSFET. Usually, a body voltage which is a reverse bias relative to the source region (in other words, Vbs less than 0) is applied to the body region of the SOI-MOSFET. As indicated by the characteristics T1, the threshold voltage Vth increases as the absolute value of the body bias voltage Vbs increases. The minimum value of the threshold voltage Vth in the SOI-MOSFET is obtained when the body bias voltage Vbs is 0 V, being about 0.4 V in the example shown in FIG. 53.
In contrast to this, in the SOI-DTMOSFET, since the gate electrode and the body region are connected to each other, a body voltage which is a forward bias relative to the source region (in other words, Vbs greater than 0) is applied to the body region of the SOI-DTMOSFET. In FIG. 53, the threshold voltage Vth of the SOI-DTMOSFET is obtained as a voltage value (about 0.3 V) at an intersection of the characteristics T1 and characteristics T2 (VGS=VBS). As compared with the minimum value, about 0.4 V, of the threshold voltage Vth in the SOI-MOSFET, it can be seen that the threshold voltage Vth is reduced in the SOI-DTMOSFET.
In the background-art DTMOSFET, however, the impurity diffusion region 111 for connecting the metal plug 114 and the body region 115 is formed in the element formation region of the SOI substrate 101, as shown in FIG. 50. Alternatively, as shown in FIG. 51, part of the metal plug 114 which exists inside the silicon layer 104 is formed in the element formation region of the SOI substrate 101.
Therefore, since a space to form a gate-body contact region such as the impurity diffusion region 111 is needed in the silicon layer 104, the area of the element formation region increases by the width of the gate-body contact region (i.e., an area penalty AP 100 of FIGS. 50 and 51). As a result, there arises a problem of an increase in chip area.
The present invention is directed to a semiconductor device. According to a first aspect of the present invention, the semiconductor device comprises: an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; an isolation insulating film formed in the semiconductor layer in an isolation region of the SOI substrate; a body region selectively formed in the semiconductor layer in an element formation region of the SOI substrate defined by the isolation insulating film; a gate electrode formed on the body region with a gate insulating film interposed therebetween; an interlayer insulating film covering the isolation insulating film and the gate electrode; a contact hole so selectively formed in the interlayer insulating film as to expose part of the gate electrode and overlap in plane view part of the isolation insulating film; and a connection body including a conductor formed in the contact hole, for electrically connecting the gate electrode and the body region, and in the semiconductor device of the first aspect, at least part of a bottom surface of the connection body overlaps in plane view the isolation insulating film.
Preferably, in the semiconductor device of the first aspect, the conductor is a metal plug.
Preferably, in the semiconductor device of the first aspect, the conductor is a semiconductor in which an impurity is introduced.
Preferably, in the semiconductor device of the first aspect, the isolation insulating film is a full-isolation insulating film formed extending from an upper surface of the semiconductor layer to an upper surface of the insulating layer.
Preferably, in the semiconductor device of the first aspect, the isolation insulating film is a partial-isolation insulating film having a bottom surface which does not reach an upper surface of the insulating layer.
Preferably, the semiconductor device of the first aspect further comprises a sidewall formed on a side surface of the gate electrode.
According to a second aspect of the present invention, in the semiconductor device of the first aspect, the whole of the bottom surface of the connection body overlaps the isolation insulating film below the contact hole.
According to a third aspect of the present invention, in the semiconductor device of the first aspect, part of the bottom surface of the connection body overlaps the isolation insulating film below the contact hole.
According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, the contact hole is formed above an upper surface of the semiconductor layer.
According to a fifth aspect of the present invention, in the semiconductor device of the fourth aspect, the gate electrode has a first semiconductor layer of a first conductivity type, and the connection body has a second semiconductor layer of a second conductivity type which is different from the first conductivity type, the semiconductor device further comprising an insulating film formed between the first semiconductor layer and the second semiconductor layer.
According to a sixth aspect of the present invention, the semiconductor device of any one of the first to fifth aspects further comprises a barrier film formed in an interface between the connection body and the body region.
According to a seventh aspect of the present invention, in the semiconductor device of any one of the first to sixth aspects, the gate electrode is a gate electrode having light transmissivity.
According to an eighth aspect of the present invention, the semiconductor device comprises: an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order, having a first element formation region and a second element formation region which are isolated from each other by an isolation region; an isolation insulating film formed in the semiconductor layer in the isolation region; a first semiconductor element formed in the first element formation region, having a first body region selectively formed in the semiconductor layer and a first gate electrode formed on the first body region with a first gate insulating film interposed therebetween; a second semiconductor element formed in the second element formation region, having a second body region selectively formed in the semiconductor layer and a second gate electrode formed on the second body region with a second gate insulating film interposed therebetween; an interlayer insulating film covering the isolation insulating film and the first and second gate electrodes; a contact hole so selectively formed in the interlayer insulating film as to expose part of the first gate electrode and part of the second gate electrode; and a connection body including a conductor formed in the contact hole, for electrically connecting the first and second gate electrodes and the first and second body regions.
According to a ninth aspect of the present invention, in the semiconductor device of the eighth aspect, at least part of a bottom surface of the connection body overlaps in plane view the isolation insulating film.
Preferably, in the semiconductor device of the ninth aspect, the whole of the bottom surface of the connection body overlaps the isolation insulating film.
According to a tenth aspect of the present invention, the semiconductor device comprises: an SOI substrate of multilayered structure in which a semiconductor substrate, an insulating layer and a semiconductor layer are layered in this order; an isolation insulating film formed in the semiconductor layer in an isolation region of the SOI substrate; a body region selectively formed in the semiconductor layer in an element formation region of the SOI substrate defined by the isolation insulating film; a gate electrode formed on the body region with a gate insulating film interposed therebetween; and bias generation means connected between the body region and the gate electrode, for limiting a body voltage which is to be applied to the body region to 0.6 V or lower.
According to an eleventh aspect of the present invention, the semiconductor device of the tenth aspect further comprises: an interlayer insulating film covering the isolation insulating film and the gate electrode; a contact hole so selectively formed in the interlayer insulating film as to expose part of the gate electrode and overlap in plane view part of the isolation insulating film; and a connection body including a conductor formed in the contact hole, being connected to the body region, wherein at least part of a bottom surface of the connection body overlaps in plane view the isolation insulating film below the contact hole.
Preferably, the semiconductor device of the eleventh aspect further comprises: a sidewall made of an insulating film for preventing the gate electrode and the conductor from coming into electrical contact.
In the semiconductor device of the first aspect of the present invention, since at least part of the connection body is formed in the isolation region, it is possible to avoid or suppress generation of an area penalty which is generated when the connection body is formed in the element formation region.
In the semiconductor device of the second aspect of the present invention, since the whole connection body is formed in the isolation region, it is possible to completely avoid generation of the area penalty which is generated when the connection body is formed in the element formation region.
In the semiconductor device of the third aspect of the present invention, since part of the connection body is formed in the isolation region, it is possible to suppress generation of the area penalty which is generated when the connection body is formed in the element formation region. Moreover, since the contact area between the connection body and the body region increases, the contact resistance therebetween decreases.
In the semiconductor device of the fourth aspect of the present invention, since it is not necessary to etch the semiconductor layer to form the contact hole inside an upper surface of the semiconductor layer, it is possible to avoid a damage of the semiconductor layer due to the etching.
In the semiconductor device of the fifth aspect of the present invention, since the insulating film is interposed between the first and second semiconductor layers which have different conductivity types, it is possible to avoid formation of a pn junction between the first and second semiconductor layers.
In the semiconductor device of the sixth aspect of the present invention, it is possible to suppress thermal diffusion of atoms constituting the connection body into the body region through various heat treatments in the manufacturing process.
The semiconductor device of the seventh aspect of the present invention can be used as a photosensor.
In the semiconductor device of the eighth aspect of the present invention, since the first semiconductor element and the second semiconductor element share one connection body, it is possible to achieve size-reduction of the semiconductor device as compared with a case where the connection bodies are individually formed.
In the semiconductor device of the ninth aspect of the present invention, since at least part of the connection body is formed in the isolation region, it is possible to avoid or suppress generation of the area penalty which is generated when the connection body is formed in the element formation region.
In the semiconductor device of the tenth aspect of the present invention, since the bias generation means limits the body voltage to 0.6 V or lower even if a voltage of 0.6 V or higher is applied to the gate electrode, it is possible to prevent a parasitic bipolar transistor from being driven.
In the semiconductor device of the eleventh aspect of the present invention, since at least part of the connection body is formed in the isolation region, it is possible to avoid or suppress generation of the area penalty which is generated when the connection body is formed in the element formation region.
An object of the present invention is to provide a semiconductor device which can avoid or suppress generation of an area penalty accompanying formation of the gate-body contact region inside the silicon layer in the SOI-DTMOSFET.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.